This application claims priority to Korean Patent Application No. 2001-65334, filed on Oct. 23, 2001, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to memory devices and, more particularly, to a semiconductor memory device to which two power supply voltages are applied.
2. Discussion of Related Art
A block diagram of a conventional SRAM is illustrated in FIG. 1.
Referring to FIG. 1, a plurality of wordlines WL1, WL2, WL3, WL4, . . . are provided in a memory cell array 1. A plurality of bitlines BL1, {overscore (BL1)}, BL2, {overscore (BL2)}, . . . are arranged to intersect these wordlines in the memory cell array 1.
Adjacent bitlines constitute bitline pairs. For example, bitlines BL1 and {overscore (BL1)} constitute a bitline pair, and bitlines BL2 and {overscore (BL2)} constitute a bitline pair. A memory cell 2 (shown by a hatched potion in FIG. 1) is arranged at respective intersections of the wordlines and the bitlines. A power supply line 3 and a ground line 4 are connected to the memory cell array 1. A power supply voltage VCC (hereinafter this voltage is regarded as a high or xe2x80x98Hxe2x80x99 level voltage) applied to the supply line 3 and a ground voltage VSS (hereinafter this voltage is regarded as a low or xe2x80x98Lxe2x80x99 level voltage) applied to the ground line 4 are applied to each memory cell 2. A row decoder 5, a column decoder 6, and an input/output circuit 8 are provided in relation to the memory cell array 1. The row decoder 5 decodes a row address applied through an address input line 7 to select one of the wordlines, and applies a voltage of H level to the selected wordline. The input/output circuit 8 includes a plurality of switching circuits each corresponding to their bitline pairs, and one or a plurality of sense amplifiers disposed between an input/output line 9 and the switching circuits. The column decoder 6 decodes a column address applied through the address input line 7 to select one of the switching circuits. The input/output line 9 is connected to a data input/output pad (not shown) through an output driver circuit (not shown). Therefore, one of the memory cells 2 is selected by the row decoder 5 and the column decoder 6.
Referring to FIG. 2, the memory cell 2 of FIG. 1 includes NMOS transistors 21, 22, 25, and 26 and PMOS transistors 23 and 24. The NMOS transistors 25 and 26 act as transfer gates, and the PMOS transistors 23 and 24 act as load elements. The NMOS transistor 21 is coupled between an ND1 node and a ground line 4, and the NMOS transistor 22 is coupled between an ND2 node and the ground line 4. Gate electrodes of the NMOS transistors 21 and 22 are connected to the ND2 and ND1 nodes, respectively. The PMOS transistor 23 is coupled between the power supply line 3 and the ND1 node, and the PMOS transistor 24 is coupled between the power supply line 3 and the ND2 node. Gate electrodes of the PMOS transistors 23 and 24 are connected to the ND2 and ND1 nodes, respectively. The NMOS transistor 25 is coupled between a bitline BLn and the ND1 node, and the NMOS transistor 26 is coupled between a bitline {overscore (BLn)} and the ND2 node. Gate electrodes of the NMOS transistors 25 and 26 are commonly coupled to a wordline WLn.
A writing operation of the SRAM will be described hereinbelow with reference to FIG. 1 and FIG. 2.
A wordline WLn is selected by the row decoder 5. A voltage of H level is applied to the wordline WLn, turning on the transistors 25 and 26. Out of the switching circuits in the input/output circuit 8, a switching circuit corresponding to the bitline pair BLn and {overscore (BLn)} is rendered conductive by the column decoder 6. Assuming that as write data, a voltage of L level is applied to the bitline {overscore (BLn)} and a voltage of H level is applied to the bitline BLn, the ND1 node of FIG. 2 attains an H level and the NMOS transistor 22 is turned on. As a result, the potential at the ND2 node is at an L level and the NMOS transistor 21 is turned off. Because the ND1 node is at H level and the ND2 node is at L level, the PMOS transistor 23 is turned on and the PMOS transistor 24 is turned off. A potential at the ND1 node is pulled up through the PMOS transistor 23 acting as a load element to maintain the H level. The potential of the ND1 node is set to H level, and the potential of the node ND2 is set to L level. This state is regarded as the state in which the memory cell 2 stores logic xe2x80x9c1xe2x80x9d. On the other hand, assuming that a voltage of L level is applied to the bitline BLn and a voltage of the H level is applied to the bitline {overscore (BLn)}, an operation opposite to the above operation is carried out. That is, the NMOS transistor 21 is turned on and the NMOS transistor 22 is turned off. Accordingly, the potential at the ND1 node is set to L level, and the potential at the ND2 node is set to H level. This state is regarded as the state in which logic xe2x80x9c0xe2x80x9d is stored.
The SRAM shown in FIG. 1 is divided into a cell area (e.g., a memory cell array) for storing data, a peripheral circuit area (row and column selection circuits, switch circuits, sense amplifiers, write drivers, data input/output buffers, etc.) for writing/reading data to/from a memory cell, and a data input/output area (e.g., pad drivers) for connecting the SRAM with an external interface. A first power supply voltage is applied to the cell area and the peripheral circuit area, while a second power supply voltage is applied to the data input/output area. The first power supply voltage has the same level as that of the second power supply voltage in a normal write/read operation mode. However, the first and second power supply voltages are externally applied through different power supply pins. An example of a memory device employing this power supply method is disclosed in the specification xe2x80x9cK6T8008C2Mxe2x80x9d published by Samsung Electronics Co., Ltd., in February 2002. A power supplied to a memory is divided according to circuit areas, which is aimed at preventing poor operations of circuits in the peripheral circuit area and checking an overcurrent region. Generally, the poor operations occur when a power supply voltage applied to a data input/output area is lowered (e.g., noise) by large consumed current in a chip operation. The overcurrent region can be checked by measuring currents respectively used in the data input/output areas.
In the case of an SRAM having a divided power supply system, a wafer burn-in test operation mode (hereinafter referred to as xe2x80x9cburn-in test operation modexe2x80x9d) suffers from several problems. The term xe2x80x9cburn-in testxe2x80x9d means that failure of a weak cell is induced in an early stage by applying excessive stresses to the memory cell with the use of a high power supply voltage. In the burn-in test operation mode, a relatively higher voltage (e.g., 5V or higher) is applied to an SRAM compared with a normal operation mode. In this case, the memory cell may be damaged by an instantaneous overcurrent. This will be described more fully with reference to FIG. 3.
Since a power supply voltage is equivalently applied to a cell area and a peripheral circuit area, a high voltage of 5V is applied to a wordline WLn, a bitline BLn or {overscore (BLn)}, and a memory cell in the burn-in test operation mode, as shown in FIG. 3. It is assumed that as write data, a voltage of 0V is applied to the bitline BLn and a voltage of 5V is applied to the bitline {overscore (BLn)}. In this assumption, an ND1 node must be set to a voltage of L level and an ND2 node must be set to a voltage of H level. In the wafer burn-in test operation, the amount of current flowing through a resistance element of a ground line 4 is higher than in a normal write operation. Thus, the resistance element prevents the ND1 node from sufficiently attaining to a ground voltage. The ND1 node is set to a voltage corresponding to the voltage drop caused by the resistance element of the ground line 4, so that the NMOS transistor 22 is not sufficiently turned off. For that reason, a DC current path is formed between a power supply line 3 and the ground line 4 through the PMOS transistor 24 and the NMOS transistor 22. Since, similar to the ND1 node, the ND2 node is not sufficiently set to a voltage of H level, a DC current path is also formed between the power supply line 3 and the ground line 4 through the PMOS transistor 23 and the NMOS transistor 21.
A latch-up phenomenon, which tends to occur during the burn-in test operation mode, causes the DC current paths to be continuously formed between the power supply line 3 and the ground line 4. Therefore, in the burn-in test operation mode, normal cells as well as weak cells may be damaged by an instantaneous overcurrent that is generated by the latch-up phenomenon.
The present invention addresses the above-described disadvantages. It is a feature of the invention to provide a semiconductor memory device which prevents a latch-up phenomenon of a memory cell in a wafer burn-in test operation mode.
Another feature of the invention is to provide a semiconductor memory device having a power supply system in which a first power supply voltage is applied to a cell area and a data input/output area and a second power supply voltage is applied to a peripheral circuit area.
Still another feature of the invention is to provide a semiconductor memory device which efficiently applies a stress to memory cells.
Further another feature of the invention is to provide a test method which efficiently applies a stress to memory cells.
To achieve these and other features, the present invention provides a novel semiconductor memory device. According to an aspect of the invention, a semiconductor memory device includes a storage area for storing data, a peripheral circuit area for writing/reading data to/from the storage area, and a data input/output area for interfacing with external devices. The data input/output area is coupled to the peripheral circuit area. During a wafer burn-in test operation mode, a first operation voltage is applied to the storage area and a second operation voltage is applied to the peripheral circuit area. The second operation voltage is lower than the first operation voltage. In this case, the first operation voltage is used as an operation voltage of the data input/output area. In the case where a normal write/read operation is carried out, the first operation voltage is equal to the second operation voltage.
According to another aspect of the invention, a semiconductor memory device includes a first power supply pad, a second power supply pad, a cell area for storing data, a peripheral circuit area for writing/reading data to/from the cell area, a data input/output area for interfacing with external devices, a first power supply line for transferring a first power supply voltage applied to the first power supply pad to the cell area, a second power supply line for transferring a second power supply voltage applied to the second power supply pad to the peripheral circuit area, and a third power supply line for transferring the first power supply voltage applied to the first power supply pad to the data input/output area. The data input/output area is coupled to the peripheral circuit area. The first and third power supply lines are coupled to the first power supply pad, and the second power supply line is coupled to the second power supply pad. During a wafer burn-in test operation mode, the first power supply voltage applied to the first power supply pad is higher than the second power supply voltage applied to the second power supply pad.
According to still another aspect of the invention, a semiconductor memory device, i.e., an SRAM, includes a first power supply pad, a second power supply pad, a cell area for storing data, a peripheral circuit area for writing/reading data to/from the cell area, and a data input/output area for interfacing with external devices. The data input/output area is coupled to the peripheral circuit area. A first power supply line is disposed to transfer a first power supply voltage applied to the first power supply pad to the peripheral circuit area. A second power supply line is disposed to transfer a second power supply voltage applied to the second power supply pad to the data input/output area. A third power supply line is disposed to transfer one of the first and second power supply voltages to the cell area. In response to a test enable signal for indicating a wafer burn-in test operation mode, a switching circuit connects the third power supply line with one of the first and second power supply pads. When the test enable signal is activated, the third power supply line is coupled to the second power supply pad. When the test enable signal is inactivated, the third power supply line is coupled to the first power supply pad. Particularly, during the wafer burn-in test operation mode, the second power supply voltage applied to the second power supply pad is higher than the first power supply voltage applied to the first power supply pad.
According to a further aspect of the invention, the invention provides a test method of a semiconductor device including a storage area for storing data, a peripheral circuit area for writing/reading data to/from the storage area, and a data input/output area that is coupled to the peripheral circuit area and interfaces with external devices. In order to carry out the test method, the semiconductor memory device enters a wafer burn-in test operation mode. Data is written to the storage area by applying a first operation voltage to the storage area and applying a second operation voltage to the peripheral circuit area. In this case, the second operation voltage is lower than the first operation voltage.